1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to the fabrication of highly sophisticated field effect transistors, such as MOS transistor structures, requiring highly doped shallow junctions and a low series resistance.
2. Description of the Related Art
The manufacturing process for integrated circuits continues to improve in several ways, driven by the ongoing efforts to scale down the feature sizes of the individual circuit elements. Presently, and in the foreseeable future, the majority of integrated circuits are and will be based on silicon devices due to the high availability of silicon substrates and due to the well-established process technology that has been developed over the past decades. A key issue in developing integrated circuits of increased packing density and enhanced performance is the scaling of transistor elements, such as MOS transistor elements, to provide the immense number of transistor elements that may be necessary for producing complex integrated circuits, such as CPUs, memory devices, mixed signal devices and the like. One important aspect in manufacturing field effect transistors having reduced dimensions is the reduction of the length of the gate electrode that controls the formation of a conductive channel separating the source and drain regions of the transistor. The source and drain regions of the transistor element are conductive semiconductor regions including dopants of an inverse conductivity type compared to the dopants in the surrounding crystalline active region, e.g., a substrate or a well region.
Although the reduction of the gate length results in smaller and faster transistor elements, it turns out, however, that a plurality of issues are involved to maintain proper transistor performance for a reduced gate length. One challenging task in this respect is the provision of shallow junction regions, i.e., source and drain extension regions and drain and source regions connecting thereto, which nevertheless exhibit a high conductivity so as to minimize the resistivity in conducting charge carriers from the source via the channel and to the drain region.
Consequently, sophisticated implantation techniques are frequently applied in order to form very shallow yet moderately highly doped drain and source extension regions with a desired minimal lateral offset to the channel region, which is typically accomplished on the basis of appropriate offset spacer elements formed on the gate electrode structure. Furthermore, in order to adjust transistor characteristics, typically counter-doped regions or halo regions may be provided adjacent to the drain and source extension regions and adjacent to the channel region, which may require tilted implantation processes. Thereafter, the drain and source regions may be formed on the basis of an increased lateral offset obtained by a corresponding sidewall spacer structure, wherein typically a high concentration of the drain and source dopant species is incorporated so as to appropriately connect to the drain and source extension regions. Depending on the complexity of the lateral and vertical dopant profiles, additional implantation processes may be required so as to obtain the desired transition of the dopant concentration from the extremely shallow source and drain extension regions to the actual drain and source regions.
In an attempt to further reduce the overall series resistance of the current path in the transistor devices, in addition to reducing the channel length, the resistance of portions of the drain and source regions is lowered by incorporating a metal silicide, which may typically exhibit a lower sheet resistance compared to silicon even if highly doped. In sophisticated approaches, nickel as a refractory metal is frequently used for locally increasing the conductivity of doped silicon areas due to the moderately low resistance of nickel silicide compared to other metal silicide materials. Hence, nickel silicide is formed in surface areas of the drain and source regions and possibly in gate electrode structures to provide superior conductivity in these areas. Upon further reducing the overall transistor dimensions, which may typically be associated with reduction of the depth of the drain and source regions, the process of forming a nickel silicide may have to be precisely controlled in order to avoid irregularities or total contact failures, such as an increase in series resistance of advanced transistors, contact punch through and the like, as will be explained in more detail with reference to FIGS. 1a-1b. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a transistor 150, which is formed in and above an active region 102A, which in turn is formed in a semiconductor layer 102. Furthermore, the semiconductor layer 102 is formed above a substrate 101, such as a silicon substrate and the like. The semiconductor layer 102 in combination with the substrate 101 may form a silicon-on-insulator (SOI) configuration when a buried insulating material (not shown) is formed below the semiconductor layer 102. In other cases, the active region may directly connect to an inversely doped crystalline semiconductor material of the substrate 101, thereby forming a bulk configuration. It should be appreciated that an active region is to be understood as a semiconductor region in the semiconductor layer 102 that is appropriately laterally delineated by corresponding isolation structures (not shown), such as a shallow trench isolation and the like. Furthermore, an active region may be understood as a device region in and above which at least one transistor is to be formed. In the manufacturing stage shown, the transistor 150 comprises drain and source regions 151 of an appropriate vertical and lateral dopant profile. Moreover, a gate electrode structure 160 is formed on the active region 102A and thus on a channel region 152, i.e., a portion of the active region 102A that is positioned laterally between the drain and source regions 151 and which is separated from an electrode material 162 of the gate electrode structure 160 by a gate dielectric material 161. Moreover, the gate electrode structure 160 comprises a spacer structure 163, which is typically comprised of one or more spacer elements in combination with corresponding etch stop liners (not shown). Moreover, in the example shown, a metal silicide, such as a nickel silicide material, is formed in the gate electrode structure 160, as indicated by 164, and also a metal silicide is formed in the drain and source regions 151, as indicated by 153.
As discussed above, in sophisticated applications, i.e., in semiconductor devices in which the transistor 150 may be formed on the basis of critical dimensions of 100 nm and significantly less, for instance 50 nm and less, typically the length of the channel region 152 may be the same order of magnitude and may thus require very sophisticated dopant profiles for the drain and source regions 151, which may have to provide high conductivity, thereby requiring high dopant levels, while at the same time generally the dopant may have to be provided with a very shallow vertical profile in order to achieve the required transistor performance. In this case, however, the incorporation of the metal silicide material 153 into the drain and source regions 151 may frequently result in significant irregularities, such as a shorting of a PN junction 151P, for instance when the metal silicide 153 may extend into the channel region 152, thereby significantly affecting the overall transistor behavior. For example, it is well known that nickel silicide may form a Schottky contact with doped silicon material, wherein the Schottky barrier may be moderately high for a weakly doped silicon material. In this case, any portion of the metal silicide region 153 extending into the moderately weakly doped channel region 152 of the active region 102A may thus substantially not contribute to the overall current flow due to the significant Schottky barrier. Consequently, the overall series resistance of the transistor 150 may be significantly increased.
The semiconductor device 100 comprising the metal silicide 153 is typically formed on the basis of the following process techniques which, however, may result in certain irregularities upon forming the metal silicide 153. The active region 102A is laterally delineated in the semiconductor layer 102 by forming isolation regions, which typically includes sophisticated lithography techniques, etch processes, deposition techniques, anneal processes and planarization techniques, for instance when sophisticated shallow trench isolations are to be provided. Prior to or after forming the isolation regions, the appropriate basic doping in the active region 102A may be established by performing implantation processes in combination with associated masking steps. Material for the gate electrode structure 160 may be formed, for instance, by deposition, oxidation and the like, depending on the desired configuration of the gate electrode structure 160. For example, in sophisticated applications, the gate dielectric material 161 may be provided as a very thin silicon oxide-based material, possibly in combination with a high-k dielectric material, while in other cases any such sophisticated gate materials may be provided in a late manufacturing stage. Moreover, the gate electrode material 162 may be provided, for instance in the form of a semiconductor material, a metal-containing material and the like. Next, sophisticated lithography techniques and patterning strategies are applied, possibly with sophisticated hard mask approaches and the like, as required for forming the gate electrode structure 160 so as to have the desired lateral dimensions. In a further advanced manufacturing stage, at least a portion of the drain and source regions 151 may be formed, for instance by ion implantation, followed by the formation of the spacer structure 163, which may act as an implantation mask for adjusting the lateral and vertical profile of a further portion of the drain and source regions 151, wherein, however, as discussed above, sophisticated implantation techniques have to be applied in order to form the drain and source regions 151 with a desired reduced depth as required. Thereafter, anneal processes may be applied, for instance based on short exposure times, in order to reduce the overall dopant diffusion, while nevertheless efficiently activating the dopant species in the drain and source regions 151. After any high temperature processes, the device 100 is prepared for the subsequent formation of the metal silicide 153, which is typically accomplished by depositing a refractory metal layer, such as a nickel layer, and initiating a chemical reaction with the underlying silicon material. During the responding heat treatment, the nickel species diffuses into the silicon material, thereby increasingly forming a metal silicide, such as a nickel silicide. Consequently, the finally obtained thickness, as indicated by 153D, of the metal silicide 153, sensitively depends on the diffusion behavior of the refractory metal, the process conditions, such as temperature, and the preparation of the surface of the device 100 prior to applying the refractory metal. Generally, an increased depth 153D is advantageous in view of providing a reduced series resistance in the transistor 150, since the metal silicide 153 has a significantly higher conductivity compared to the even highly doped drain and source regions 151. On the other hand, controlling the silicidation process so as to achieve a depth 153D which is similar to the depth of the drain and source regions 151, may be associated with a high probability of causing any short circuits of the PN junction 151P, as explained above. Consequently, in sophisticated devices, typically the silicidation process is controlled so as to reduce the risk of shorting the PN junctions 151P.
FIG. 1b schematically illustrates the device 100 in a further advanced manufacturing stage, wherein additionally the depth 153D of the metal silicide regions 153 is controlled so as to substantially avoid the shorting of the PN junctions 151P. Thus, a significantly reduced thickness 153D is obtained which, however, may result in an extremely narrow process window during the further processing when forming a contact level 120 of the device 100. When forming contact elements in a dielectric material 121 of the contact level 120, corresponding openings 122 have to be formed so as to connect to the metal silicide regions 153 in the drain and/or source regions of the transistor 150. During the complex etch process, a final stage of the metal silicide 153 has to be exposed which, however, may result in a punch through of the metal silicide 153 due to the reduced thickness 153D. In this case, the opening 122 may extend deeply into the drain and source regions 151 and may even result in a shorting of the corresponding PN junctions 151P after filling the contact opening 122 with an appropriate conductive material, such as tungsten and the like. Consequently, in sophisticated applications, the processes of forming the metal silicide 153 in the drain and source regions 151 is closely interrelated with the subsequent process for forming contact elements, thereby requiring tightly set process windows in both of these processes, which may thus result in a compromised transistor performance, while nevertheless also a certain probability of creating transistor irregularities or total contact failures may exist.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.